Formal Verification of a Processor with Memory Management Units

In this book we present the formal verification of amemory management unit which operates under specific conditions. We also present the formal verificationof a complex processor VAMP with support of addresstranslation by means of a memory management unit. The VAMP is an out-of-order 32-bit RISC CPU with a DLX instruction set, fully IEEE-compliant floating point units, and a memory unit. The VAMP also supports precise internal and external interrupts. It is modeled on the gate level and verified with respect to its specification. The subject of this book is based on the formal proof of the VAMP without address translation [Bey05] and on paper and pencil specification, implementation, and correctness proof of a memory management unit [Hil05]. The results of this work yield a formally verified gate-level implementation of the VAMP with support of address translation, with interrupts, and a cache memory interface with split instruction and data caches.

Autorentext

I.Dalinger: Born in 1979. He received PhD degree from Saarland University in 2006. Now, he is deputy vice-president for science of Saint-Petersburg State University of Civil Aviation. A.Alekhin: Born in 1983. He received MSc degree in computer science from Saarland University in 2009. Now, he works as a scientific researcher in Saarland University.

Klappentext
In this book we present the formal verification of a memory management unit which operates under specific conditions. We also present the formal verification of a complex processor VAMP with support of address translation by means of a memory management unit. The VAMP is an out-of-order 32-bit RISC CPU with a DLX instruction set, fully IEEE-compliant floating point units, and a memory unit. The VAMP also supports precise internal and external interrupts. It is modeled on the gate level and verified with respect to its specification. The subject of this book is based on the formal proof of the VAMP without address translation [Bey05] and on paper and pencil specification, implementation, and correctness proof of a memory management unit [Hil05]. The results of this work yield a formally verified gate-level implementation of the VAMP with support of address translation, with interrupts, and a cache memory interface with split instruction and data caches.