High-level SOC Modeling and Performance Estimation

The objective of this book is to provide the system designer with means (on the methodology and tools levels) to estimate system s performances and evaluate rapidly and very early the design decisions in the SoC design flow. Our work provides contributions in two main aspects: (1) On the Conceptual Level, we defined (using the UML meta-modeling concepts) modeling concepts to estimate shared resources impact on system s overall performances, by introducing the virtual node concept for scheduling and shared resources access control. Furthermore, we introduced the Communication Pattern concept for modeling the interaction between architecture elements to ensure the orthogonalization of computation and communication concerns. (2) On the Simulation Level: A SystemC simulator was written to simulate the UML models. Simulation is done at a high level of abstraction and runs faster than real time execution. The usability and capabilities of our approach are shown with an industrial use case. We modeled an LTE base station, and compared the modeling results with the real implementation

Autorentext

Chafic JABER is a research engineer at the "Commissariat à l'énergie atomique" (CEA), France. He received his PhD from Telecom ParisTech and MS in Embedded Systems from the University of Nice, France. Before, He received his masters of engineering in telecommunication from Antonin-fathers university, Lebanon.