PLL Architecture:

A phase-locked loop (PLL) is a feedback system in which a phase comparator or detector drives a voltage controlled oscillator (VCO) in a feedback loop to make the oscillator frequency (or phase) accurately track that of an applied reference frequency. A filter circuit is typically required to integrate and smooth the positive or negative error signal-and promote loop stability. A frequency divider is often included in the feedback path to establish the output frequency (within the range of the VCO) as a multiple of the reference frequency. The divider can be implemented so that the frequency multiple, N, will be either an integer or a fractional number, characterizing the PLL as an integer-N PLL or a fractional-N PLL. But if a VCO's output signal frequency were always predictable with no variation, there would be no need to use feedback control to correct the error in frequency which is known as direct digital synthesizer (DDS).

Autorentext

Mohammad Arif Sobhan Bhuiyan est actuellement professeur assistant au département d'ingénierie électrique et électronique (EEE) de l'université Xiamen de Malaisie (XMUM). Ses recherches portent sur les VLSI et les communications sans fil.