Single Event Upset in Dual- and Triple-Well SRAMs

CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the single-event response between these two technology options, however, are not well understood. This work presents a comprehensive analysis of alpha, neutron and heavy ion-induced upsets in 65-nm and 40-nm dual-well and triple-well CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technology is more vulnerable to low-LET particles, while dual-well technology is more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the Single Event Upset Reversal mechanism that reduces sensitivity at high LETs.

Autorentext

Indranil Chatterjee received his B.Tech in Electronics Engineering from West Bengal University of Technology, India and MS in Electrical Engineering from Vanderbilt University, USA where he is presently a doctoral student. His research interests include Semiconductor Reliability, Radiation Tolerance of Semiconductor Devices and Novel Devices.