SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE

Increasing the complexity of the electronic systems
leads to electronic system level modeling concept
supporting hardware and software co-design and
co-verification environment in a single framework.
SystemC, an IEEE approved electronic design
standard for system design and verification
processes, provides such an environment by supporting
a wide range of abstraction levels from system-level
to register-transfer level. In this book, two
different models of a processor core, whose
instruction set architecture is compatible with
TI MSP430 microcontroller, are designed by
employing the classical hardware modeling capability
of the SystemC. With its well-designed orthogonal
instruction set, elegant addressing modes, useful
constant generators and flexible von-Neumann
architecture, 16-bit RISC-like processor of the
MSP430 microcontroller is an ideal selection for the
SoC designs. Instruction set and addressing modes of
the designed processors are simulated thoroughly.
Moreover, original CRC programs are used to verify
the processor cores. SystemC to
hardware flow is also illustrated by synthesizing the
ALU part of the processor into a Xilinx-based
hardware.

Autorentext

He was born in 1979 and he received B.S. and M.S. degrees in Electrical and Electronics Engineering at Middle East Technical University(METU),Turkey in 2003 and 2006 respectively. He is currently pursuing his Ph.D. at METU and his main interest areas are SystemC,computer architectures,multi-processor systems and their network applications.

Klappentext

Increasing the complexity of the electronic systemsleads to electronic system level modeling conceptsupporting hardware and software co-design andco-verification environment in a single framework.SystemC, an IEEE approved electronic designstandard for system design and verificationprocesses, provides such an environment by supportinga wide range of abstraction levels from system-levelto register-transfer level. In this book, twodifferent models of a processor core, whoseinstruction set architecture is compatible withTI MSP430 microcontroller, are designed byemploying the classical hardware modeling capabilityof the SystemC. With its well-designed orthogonalinstruction set, elegant addressing modes, usefulconstant generators and flexible von-Neumannarchitecture, 16-bit RISC-like processor of theMSP430 microcontroller is an ideal selection for theSoC designs. Instruction set and addressing modes ofthe designed processors are simulated thoroughly.Moreover, original CRC programs are used to verifythe processor cores. SystemC tohardware flow is also illustrated by synthesizing theALU part of the processor into a Xilinx-based hardware.