A Genetic Algorithm for VLSI Floorplanning

VLSI design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. The classical floor planning techniques use block packing to minimize chip area, by making use of algorithms like B-TREE representation, simulated annealing. To get an optimal solution it is imperative to choose an efficient algorithm. In this work, a genetic algorithm based floorplanner has been developed.

Autorentext

Anmol Shahani completed his Bachelors of Engineering in Electronics and Telecommunication from the University of Mumbai. He will be pursuing Masters of Science in Electrical and Computer Engineering from USA. His interests include Computer Architecture, Microprocessor System Design.