Approximate multipliers for image processing

Approximate computing can decrease the design complexity with an increase in performance and power proficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability. The proposed approximation is utilized in two variants of 16-bit multipliers. Synthesis results reveal that the proposed 8 bit multiplier achieve power savings and reduces the delay compared to an exact multiplier. They have better accuracy when contrasted with existing estimated multipliers. Which are better than the previous works. Performance of the proposed multipliers is evaluated with an image processing application using Gaussian filter, where Gaussian filter with proposed approximate multiplier model achieves the highest peak signal to noise ratio(PSNR).

Autorentext

El Prof. Sridhar T.N., profesor asistente del Departamento de Ingeniería Electrónica y de Comunicaciones del Instituto de Tecnología de Cambridge, Devanahalli, distrito rural de Bangalore, ha impartido muchas asignaturas a estudiantes de ingeniería. Se ha especializado en el diseño de VLSI y en los sistemas embebidos.