CAD for Hardware Security

This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC verification experts. Readers will gain a comprehensive understanding of SoC security vulnerabilities and how to overcome them, through an efficient combination of proactive countermeasures and a wide variety of CAD solutions.

Offers techniques to protect hardware designs from a variety of vulnerabilities using CAD Provides a comprehensive introduction to current SoC security vulnerabilities at different levels of abstraction Discusses CAD-based approaches and their application to SoC security issues at various levels of design abstraction

Autorentext

Mark Tehranipoor received his Ph.D. from the University of Texas at Dallas in 2004. He is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT Security, VLSI design, test and reliability. Dr. Tehranipoor has published over 400 journal articles and refereed conference papers and has given about 200 invited talks and keynote addresses. He has published 11 books and more than 20 book chapters. He is a recipient of a dozen best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair. He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and Associate Editor for JETTA, JOLPE, IEEE TVLSI and ACM TODAES. Prior to joining UF, Dr. Tehranipoor served as the founding director for CHASE and CSI centers at the University of Connecticut. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS). Dr. Tehranipoor is a Fellow of the IEEE, a Golden Core Member of IEEE CS, and Member of ACM and ACM SIGDA. Nidish Vashistha is currently an R&D Yield Enhancement and Physical Failure Analysis Engineer for developing next-generation NAND memory devices at Micron. He received his Ph.D. in Electrical and Computer Engineering in 2022 and MS in 2017 from the University of Florida. His previous work experience includes working as a Product and Test Engineering Intern at Renesas Electronics America and RF Engineer at Ericsson. His research area includes secure integrated circuits design and trust validation using SEM nano-imaging, computer vision, and machine learning. Besides, he has contributed his research expertise to develop an ecosystem for trusted microelectronics by performing vulnerability risk assessment and mitigation through blockchain. He has authored several papers, articles, and book chapters in his research areas. His research work was recognized as an invited paper in IEEE ITC 2019, nominated for the best paper award in IEEE HOST 2019, and audience choice best demo award in IEEE HOST 2022. In addition, he is a co-inventor of Trojan Scanner. He has been an IEEE member for 14 years. He also serves as a peer reviewer in HaSS, ACM JETCS, TCAS-1, and TSP journals. Farimah Farahmandi is an assistant professor in the Department of Electrical andComputer Engineering at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran, in 2010 and 2013, respectively. Her research interests include design automation of System-on-Chips and energy-efficient systems, formal verification, hardware security validation, and post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and several publications in premier ACM/IEEE journals and conferences, including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards, including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, a nomination for the Best Paper Award in ASPDAC

Inhalt

Introduction.- CAD for Information Leakage Assessment.- CAD for Power Side Channel Leakage Assessment.- CAD for Electromagnetic Radiation Leakage Assessment.- CAD for Timing Leakage Assessment.- CAD for Fault Injection Attack Analysis.- CAD for Obfuscation.- CAD for Watermarking.- CAD for HW Metering.- CAD for Detecting HLS Vulnerabilities.- CAD for Counterfeit Detection and Prevention.- CAD for Trojan Detection and Prevention.- CAD for Physical Assurance.- CAD for Anti-Probing.- CAD for Formal Security Verification.- CAD for Reverse Engineering.