Configurable Cache Tuning

In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics are dependent on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, this book presents a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique.

Autorentext

Pablo Viana is a Professor of Computer Science at the Federal University of Alagoas. He received a M.S. and Ph.D. degrees from the Federal University of Pernambuco in 2002 and 2006, respectively. His interests are in the areas of architecture for high-performance computing and human interface devices.