FPGA implementation of Hopfield Neural Network

This work was to establish whether it was possible to achieve a reasonable speedup by implementing FPGA based Hopfield neural networks for some simple constraint satisfaction problems. The results are significant our initial implementation using standard Xilinx FPGAs yielded 2-3 orders of magnitude speedup over the Sun Blade 2000 workstation comes with 1.2-GHz version of the 64-bit UltraSPARC III Cu processor. The main problem with the work to date is that the problems are both unrealistically small and simplistic. That is the constraints on the N-Queen problem are simpler than those found in many real world scheduling applications. Thus, it is not clear whether we will be able to optimize the neuron structure for more complex problems since the weights matrix may not contain as many zero elements. Thus a new method for speed improvement of Hopfield neural networks for solving constraint satisfaction problems using Field Programmable Gate Arrays (FPGAs) was proposed and implemented.

Autorentext

Avvaru Srinivasulu was born in Andhrapradesh, India, in 1985. He received the B.Tech degree in Electronics and Control Engineering in 2006 and M.Tech degree in Instrumentation and Control Systems in 2008 from Jawaharlal Nehru Technological University, Hyderabad.