Fundamental optimized AES algorithm design in FPGA

This book mainly focuses research in recent area of Network Security algorithm and its optimized design in area optimization domain. This book is intended for a broad range of readers who will benefits from an understanding of AES algorithm and its overall process associated with VHDL software implementation on Xilinx FPGA device. This includes students and professionals in the field of data processing and data communication, designers and implementers and data communication and networking customers and managers. This book is designed to be self -contained .For reader with little or more background of cryptographic algorithms.

Autorentext

Prof. H.S.Deshpande, der als Assistenzprofessor am S.K.N.Sinhgad College of Engineering arbeitet, schloss sein ME(Electronics Engineering) mit einem Projekt ab, das auf der optimierten Implementierung von Netzwerksicherheitsalgorithmen in FPGA basiert. Die Optimierung erfolgte im Bereich der Reduzierung der Anzahl der Slices durch die bevorzugte Verwendung der statischen RAM-Struktur in FPGA CLBs.