Hardware Acceleration of EDA Algorithms

This text covers the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. In it, widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs.

Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.

Provides guidelines on whether to use GPUs or FPGAs when accelerating a given EDA algorithm, with validation by a concrete example implemented on both platforms Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups from 30X to 800X Presents techniques in a way that the reader can use example algorithms presented to determine how best to accelerate their specific EDA algorithm Discusses an automatic approach to generate GPU code, given regular uniprocessor code Includes supplementary material: sn.pub/extras

Klappentext

Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs

Kanupriya Gulati

Sunil P. Khatri

This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms.

This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition.

In particular, this book:

• Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms;

• Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X;

• Helps the reader by presenting example algorithmswhich may be used by the reader to determine how best to accelerate their specific EDA algorithm;

• Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints;

• Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.

  Inhalt
  Alternative Hardware Platforms.- Hardware Platforms.- GPU Architecture and the CUDA Programming Model.- Control Dominated Category.- Accelerating Boolean Satisfiability on a Custom IC.- Accelerating Boolean Satisfiability on an FPGA.- Accelerating Boolean Satisfiability on a Graphics Processing Unit.- Control Plus Data Parallel Applications.- Accelerating statistical static Timing Analysis Using Graphics Processors.- Accelerating Fault Simulation Using Graphics Processors.- Fault Table Generation Using Graphics Processors.- Accelerating Circuit Simulation Using Graphics Processors.- Automated Generation of GPU Code.- Automated Approach for Graphics Processor Based Software Acceleration.- Conclusions.