High-Performance Computing on the Intel® Xeon Phi(TM)

The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors' first-hand optimization experience.

The material is organized in three sections. The first section, Basics of MIC, introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment. Next, the section on Performance Optimization explains general MIC optimization techniques, which are then illustrated step-by-step using the classical parallel programming example of matrix multiplication. Finally, Project development presents a set of practical and experience-driven methods for using parallel computing in application projects, including how to determine if a serial or parallel CPU program is suitable for MIC and how to transplant a program onto MIC.

This book appeals to two main audiences: First, software developers for HPC applications it will enable them to fully exploit the MIC architecture and thus achieve the extreme performance usually required in biological genetics, medical imaging, aerospace, meteorology and other areas of HPC. Second, students and researchers engaged in parallel and high-performance computing it will guide them on how to push the limits of system performance for HPC applications.

Explains HPC from general optimization and parallel programming concepts to the details of MIC programming Illustrates all concepts with both a standard example and extracts of real-world applications Written by a team closely involved in the development of the Intel® Xeon Phi™ coprocessor, the backbone of the fastest supercomputer in the world (Tianhe-2) Includes supplementary material: sn.pub/extras

Autorentext
Endong Wang is the Director of the State Key Laboratory of High-Efficiency Server and Storage Technology at the Inspur-Intel China Parallel Computing Joint Lab and Senior Vice President of the Inspur Group Co., Ltd. Qing Zhang is the lead engineer of the Inspur-Intel China Parallel Computing Joint Lab and with his team he was among the first to work with the development environment of the Intel® Xeon processor and Intel® Xeon Phi™ coprocessor. Together they have several years of experience in HPC programming.

Inhalt
Part 1: Fundamental Concepts of MIC.- 1 High-performance Computing( HPC) with MIC.- 2 MIC Hardware and Software Architecture.- 3 The First MIC ExampleComputing Pi.- 4 Fundamentals of Open MP and MPI Programming.- 5 MIC Programming.- 6 Debugging and Profiling Tools for MIC.- 7 Intel MIC MKL Library.- Part 2: Performance Optimization.- 8 Performance Optimization on MIC.- 9 MIC Optimization Example: Matrix Multiplication.- Part 3: Project Development.- 10 Developing HPC Applications Based on the MIC.- 11 HPC Applications Based on MIC.