Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time.

Discusses the effects of radiation on modern integrated circuits Provides a comprehensive overview of state-of-the art fault tolerance techniques based on software, hardware, and hybrid techniques Introduces novel hybrid fault tolerance techniques for reconfigurable FPGAs and ASICs Performs fault injection campaigns by simulation, bitstream fault injection, and radiation experiments Enables readers to use techniques with lower performance degradation, area occupation, and memory usage Includes supplementary material: sn.pub/extras

Inhalt

Introduction.- Background.- Fault Tolerance Techniques for Processors.- Proposed Techniques to Detect Transient Faults in Processors.- Simulation Fault Injection Experimental Results.- Configuration Bitstream Fault Injection Experimental Results.- Radiation Experimental Results.- Conclusions and Future Work.