Low Power Digital Design using Asynchronous Logic

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Details

The need for low power design is motivated by several factors, such as the emergence of portable systems, thermal considerations, reliability issues, and, most importantly, environmental concerns. Lots of power is wasted in an electronic device when the system is idle. This book introduces a new method of achieving low power by reducing the dependency of the clock signal in the design. It mainly focuses on obtaining low power by implementing asynchronous logic.

Autorentext

This work on Low power digital design using asynchronous logic is my first publication. I did this work as a thesis during my Masters in Electrical Engineering in SJSU. The main reason I was interested in this topic had an environmental concern and that was the amount of power that could be saved by going in for asynchronous design.

Weitere Informationen

  • Allgemeine Informationen
    • Sprache Englisch
    • Herausgeber LAP LAMBERT Academic Publishing
    • Gewicht 155g
    • Untertitel Moving towards clock-less design
    • Autor Sathish Vimalraj Antony Jayasekar
    • Titel Low Power Digital Design using Asynchronous Logic
    • Veröffentlichung 10.10.2011
    • ISBN 3846518441
    • Format Kartonierter Einband
    • EAN 9783846518441
    • Jahr 2011
    • Größe H220mm x B150mm x T6mm
    • Anzahl Seiten 92
    • Auflage Aufl.
    • GTIN 09783846518441

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