Network-on-Chip Architectures

NoC architectures are seen as a possible solution to burgeoning global wiring delays in many-core chips, and this work deals with the main issues that need to be resolved in performance, energy efficiency, reliability, variability and silicon area consumption.

[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel's very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

A comprehensive study of Network-on-Chip architectures for multi-core chips Analysis of complex interplay between various design evaluation metrics Detailed look at both macro- and micro-architectural design issues Innovative solutions for increased reliability and process variability tolerance

Klappentext

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.

Inhalt
MICRO-Architectural Exploration.- A Baseline NoC Architecture.- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39].- RoCo: The RowColumn Decoupled Router A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40].- Exploring FaultoTolerant Network-on-Chip Architectures [37].- On the Effects of Process Variation in Network-on-Chip Architectures [45].- MACRO-Architectural Exploration.- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15].- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43].- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44].- Digest of Additional NoC MACRO-Architectural Research.- Conclusions and Future Work.