The Student's Guide to VHDL

Informationen zum Autor Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM. Klappentext The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for Computer Organization and Digital Design courses. Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition (SG2E), we plan to include a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modelling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study will better serve the educational market. Zusammenfassung A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow! starting from high-level design and proceeding through detailed design and verification! synthesis! FPGA place and route! and final timing verification. Inhaltsverzeichnis Preface1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Subprograms7 Packages and Use Clauses8 Aliases9 Resolved Signals10 Generics11 Components12 Generate Statements13 Design for Synthesis14 Case Study: System Design using the Gumnut CoreA Standard PackagesB VHDL SyntaxC Differences Among VHDL VersionsD Answers to ExercisesReferencesIndex...

Autorentext

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Klappentext
The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for Computer Organization and Digital Design courses. Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition (SG2E), we plan to include a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modelling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study will better serve the educational market.

Zusammenfassung
A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification.

Inhalt

Preface1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Subprograms7 Packages and Use Clauses8 Aliases9 Resolved Signals10 Generics11 Components12 Generate Statements13 Design for Synthesis14 Case Study: System Design using the Gumnut CoreA Standard PackagesB VHDL SyntaxC Differences Among VHDL VersionsD Answers to ExercisesReferencesIndex