Tiling Optimizations for Parallelization

Traditionally, research on tiling optimizations mainly focuses on tessellating tiling, atomic tiles and regular tile shapes. This book studies several novel tiling techniques which are out of the scope of traditional research. In order to represent a general tiling scheme uniformly, a unified tiling representation framework is introduced. With the unified tiling representation, three tiling techniques are studied. Those techniques use tiles of irregular shapes to hide communication latency, balance workloads and enhance parallelism. This study could possibly help researchers working on compilers and high performance computing.

Autorentext

Xing Zhou, Ph.D.: Studied Computer Science at University of Illinois at Urbana-Champaign. Software Engineer at Google Inc., New York.