Verilog® Quickstart

Welcome to the world of Verilog! Once you read this book, you will join the ranks of the many successful engineers who use Verilog. I have been using Verilog since 1986 and teaching Verilog since 1987. I have seen many different Verilog courses and many approaches to learning Verilog. This book generally follows the outline of the Verilog class that I teach at the University of California, Santa Cruz, Extension. This book does not take a "cookie-cutter" approach to learning Verilog, nor is it a completely theoretical book. Instead, what we will do is go through some of the formal Verilog syntax and definitions, and then show practical uses. Once we cover most of the constructs of the language, we will look at how style affects the constructs you choose while modeling your design. This is not a complete and exhaustive reference on Verilog. If you want a Verilog reference, I suggest one of the Open Verilog International (OVI) reference manuals.

Klappentext

emVerilog® Quickstart/em is a basic, practical, introductory textbook for professionals and students alike. This book explains how a designer can be more effective through the use of the Verilog hardware description language to simulate and document a design. br/ By understanding simulation, a designer can simulate a design to see if a design works before it is built. This gives the designer an opportunity to try different ideas. Documentation allows a designer to maintain and reuse a design more easily. Verilog's intrinsic hierarchical modularity enables the designer to easily reuse portions of the design as intellectual property' or macro-cells'. br/ emVerilog® Quickstart/em presents some of the formal Verilog syntax and definitions and then shows practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. br/ emVerilog® Quickstart/em has over 100 examples that are used to illustrate aspects of the language. In the later chapters the focus is on working with modeling style and explaining why and when one would use different elements of the language. Another feature of the book is the chapter on state machine modeling. There is also a chapter on test benches and testing strategy as well as a chapter on debugging. br/ emVerilog® Quickstart/em is designed to teach the Verilog language, to show the designer how to model in Verilog and to explain the basics of using Verilog simulators.

Inhalt
1 Introduction.- Framing Verilog Concepts.- Where To Get More Information.- 2 Introduction to the Verilog Language.- Identifiers.- White Space.- Comments.- Numbers.- Text Macros.- Modules.- Semicolons.- Value Set.- Strengths.- Numbers, Values, and Unknowns.- 3 Structural Modeling.- Primitives.- Ports.- Instances.- Hierarchy.- Hierarchical Names.- 4 Behavioral Modeling.- Starting Places for Places for Blocks of Behavioral Code.- System Tasks for Printing Out Results.- Data Objects in Verilog.- Procedural Assignments.- Ports and Registers.- 5 Operators.- Binary Operators.- Unary Operators.- Reduction Operators.- Ternary Operator.- Equality Operators.- Concatenations.- Logical versus Bit-wise Operations.- Operations That Are Not Legal on Reals.- Working with Strings.- Combining Operators.- Sizing Expressions.- 6 Working with Behavioral Modeling.- Continuous Assignment.- Event Control.- The if Statement.- The case Statement.- Loops.- Procedural Continuous Assignments.- tasks.- functions.- A Reminder about Ports and Registers.- Modeling with inout Ports.- Named Blocks.- The disable Statement.- When is a Simulation Done.- 7 User-Defined Primitives.- Combinatorial UDPs.- Sequential UDPs.- UDP Instances.- The Final Details.- 8 Parameterized Modules.- n-Bit Mux.- n-Bit Adder.- n By m Mux.- n By m Ram.- Using Parameterized Modules.- 9 State Machines.- State Machine Types.- State Machine Modeling Style.- State Encoding Methods.- Default Conditions.- Implicit State Machines.- Registered and Unregistered Outputs.- Factors in Choosing a State Machine Modeling Style.- 10 Modeling Tips.- Modeling Combinatorial Logic.- Modeling Sequential Logic.- Modeling Asynchronous Circuits.- Special-Purpose Models.- Multiplier Examples.- A Proven, Successful Approach to Modeling.- 11 Modeling StyleTrade-Offs.- Forces That Influence Modeling Style.- Learning From Other People' s Mistakes.- When To Use UDPs.- 12 Test Benches and Test Management.- to Testing.- Response-Driven Stimulus.- Test Benches for Inouts.- Loading Files into Verilog Memories.- Test Benches with No Test Vectors.- Using a Script To Run Test Cases.- Modeling BIST.- The Surround and Capture Method.- 13 Common Errors.- Mismatched Ports.- Missing or Incorrect Declarations.- Improper Use of Procedural Continuous Assignments.- Missing initial or always Blocks.- Zero-Delay always Loops.- initial Instead of always.- Missing Initialization.- Overly Complex Code.- Unintended Storage.- Timing Errors.- 14 Debugging A Design.- Overview of Functional Debugging.- Universal Techniques.- Using Waveforms.- Interactive Debugging.- Catching Problems Later in a Simulation.- Isolating Differences in Models.- Summary of Debugging.- Appendix A Gate Level Details.- Primitive Descriptions.- Logic Gates.- AND.- NAND.- OR.- NOR.- XOR.- XNOR.- Buffers.- BUF.- NOT.- BUFIFO.- BUHF1.- NOTIF0.- NOTIF1.- PULLDOWN.- PULLUP.- Switches.- NMOS and RNMOS.- PMOS and RPMOS.- CMOS and RCMOS.- TRAN and RTRAN.- TRANIFO and RTRANIFO.- TRANIF1 and RTRANIF1.- Instance Details.- Delays.- Delay Units.- Printing Out Time and the Timescale.- Strengths.- Strength reduction of switch primitives.- Appendix B Example Summary.