A parallel Architecture for Motion Estimation using H.264/AVC standard

Motion Estimation Architecture for parallel execution using FPGA based systems. A novel architecture proposed reduces execution time and improves throughput for Motion Estimation. This Architecture is verifed experimentally on a Xilinx based FPGA system. This was a result of ongoing research project at San Francisco State University California and a thesis for my Masters Degree in Elecrical Engineering.

Autorentext

I am a Systems Engineer working in California USA. I have a Master's in Science Degree in Electrical Engineering with particular focus in Hardware Design and FPGA Design. I have worked and implemented several Video coding projects for my company with passion for video technology