A reliable logic bist with scalable approach

We propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs.

Autorentext

A. Raghavaraju erhielt seinen M.Tech von der ANNA Universität Chennai und seinen B.Tech von der JNTU Hyderabad. Derzeit promoviert er an der K. Lakshmaiah Education Foundation, Indien. Zurzeit arbeitet er als Assoc. Prof. in der Abteilung für E.C.E., Chebrolu Engg. College. Er hat mehrere Arbeiten in internationalen Fachzeitschriften und scopus-indizierten Journalen veröffentlicht.