A Synergistic Framework for Hardware IP Privacy and Integrity Protection

This book proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined to provide a formal security guarantee.

Analyzes comprehensively major Integrated Circuit IP privacy and security issues Introduces a synergistic framework to address the major IP security and privacy issues from different IP design stages Provides rigorous mathematical modeling for primary IP violations to enable formal analysis and protection

Autorentext

Meng Li received his B.S. degree in Microelectronics from Peking University, China in 2013 and his Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2018. He is currently a research scientist in Facebook Inc. His research interests include deep learning acceleration, hardware-oriented security and reliability. Meng Li received many awards, including the Margarida Jacome Dissertation Prize from the University of Texas at Austin in 2019, the EDAA Outstanding Dissertation Award in 2019, the First Place in the grand final of ACM student research competition in 2018, the Best Poster (Presentation) Award in ASPDAC Ph.D. forum in 2018, the Gold Medal in ACM ICCAD student research competition in 2017, and the University Graduate Fellowship from UT Austin in 2013. He also received the Best Paper Award in HOST 17 and GLSVLSI 18. David Z. Pan received his BS degree from Peking University and MS/PhD degrees from UCLA. He is currently Engineering Foundation Professor at the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include cross-layer IC design for manufacturing, reliability, security, machine learning in EDA, hardware acceleration, CAD for analog/mixed signal designs and emerging technologies. He has published over 360 refereed journal/conference papers and 8 US patents. He has served in many journal editorial boards and conference committees, including various leadership roles. He has received many awards, including SRC Technical Excellence Award, 18 Best Paper Awards, DAC Top 10 Author Award in Fifth Decade, ASP-DAC Frequently Cited Author Award, Communications of ACM Research Highlights, ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, IBM Faculty Award (4 times), UCLA Engineering Distinguished Young Alumnus Award, UT Austin RAISE Faculty Excellence Award, etc. He is a Fellow of IEEE and SPIE.

Inhalt

Introduction.- Practical Split Manufacturing Optimization.- IC Camouflaging Optimization and Evaluation.- Fault Attack Protection and Evaluation.- Conclusion.