An Approach to mitigate Single Event Latch Up and Soft Errors

Single Effect is a big challenge for VLSI Industries. All kind of Aircraft are suffering with this issue. So A excellent mitigation scheme is required to withstand with this issue. Keeping this issue in the mind, this book has been written. The book started with the semiconductor memories description then radiation effects and step by step to mitigation schemes. The mitigation schemes with effect at different parameters is also given with comparison so that a researcher can easily take reference and move for further research. This book is written in very easy and interesting language so that even a beginner can understand easily

Autorentext

Amarish Dubey received B.Tech in Elex.& Comm. Engg. from U.P. Technical University,INDIA. He has completed his M.Tech in Digital Design from IIT(BHU) Varanasi,India with honors.Currently he is working as an Asst.Prof in MPEC, Kanpur UP INDIA. He has more than 5 years of teaching Experience. His area of interest is VLSI Design and Fault Tolerance.