Analog Baseband Processor for a 5 GHz WLAN Receiver

Wireless technologies are progressing rapidly and becoming essentials in our life environment such as smart-phones, mobile tablet pads, and laptop computers. Increasing demand for data network connectivity has made wireless local area network (WLAN) popular. IC design in CMOS process technology also has been the key for providing low-cost single chip solutions to the mobile data communications devices. This book discusses the design of a CMOS analog baseband processor including channel-select filtering with automatic gain control (AGC) for a 5- GHz CMOS WLAN receiver. A new open-loop analog gain- control algorithm for OFDM is proposed. Channel- select filters are composed of 3rd and 4th order cascaded elliptic lowpass Gm-C filters. The AGC circuit is implemented in a 0.18 µm CMOS process using newly designed circuits including linear VGA, RMS detector, and current-mode computation circuitry. The IC design techniques and ideas in the book should be helpful to anyone in the area of CMOS analog circuit design and can be useful to the junior engineers or graduate students in the field.

Autorentext

Okjune Jeon received the B.S. degree from Korea Military Academy (Seoul, Korea, 1986), the M.S. degree from Case Western Reserve University (Cleveland, OH, 1990), and the Ph.D. degree from the University of Florida (FL, 2005), all in electrical engineering. He is presently a Principal RFIC Design Engineer at Rfaxis, Inc., Irvine, CA.