Analysis of various DCVSL Structures and Implementation of Full Adder

The Differential Cascode Voltage Switch Logic (DCVSL) is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of power dissipation, circuit delay, layout density and logic flexibility. In this paper, a detailed comparison of all the DCVSL structures are provided including the implementation of Full Adder circuit with the help of those DCVSL structures, which includes Static DCVSL, Dynamic DCVSL and Modified DCVSL. The performance analysis is done in Cadence Virtuoso 90nm CMOS Technology. The analysis of all these DCVSL structures is followed by the implementation of Full Adder. Adders are the building blocks in computer systems. Digital Computer Systems widely uses Arithmetic operations. Addition is a necessary arithmetic operation, which is also the root for arithmetic operation such as multiplication. Similarly, adding another XOR gate, the basic adder cell can be modified to function as sub-tractor, which can be used for division. Therefore, 1-bit Full Adder cell is the ultimate and simple block of an arithmetic unit of a system. So, the basic 1-bit Full Adder cell must be improved, as the performance of the digital circuits.

Autorentext

Je m'appelle Subhrajit Roy. J'ai obtenu mon diplôme de M.Tech, avec une spécialisation en conception VLSI et systèmes embarqués en 2015, à l'Institut national de technologie, Rourkela, Inde. Je travaille actuellement dans une entreprise de technologies de l'information.