ASIC Implementation of Low Power FP-AU using Reversible Logic

This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.

Autorentext

Dr. K.N. Vijeyakumar arbeitet als außerordentlicher Professor am Dr. Mahalingam College of Engineering and Technology, Coimbatore, Tamilnadu. Zu seinen Interessengebieten gehören ASIC-Design, VLSI-Design mit geringem Stromverbrauch und IC-Fertigung. Er hat mehr als 25 Forschungsarbeiten in renommierten internationalen Fachzeitschriften veröffentlicht.