Bias-Temperature-Instabilities in MOSFETs with high-k dielectrics

New MOSFET architectures are presently being developed in which dielectrics with high permittivity are introduced to replace SiO2-based dielectrics, which are at the end of the scaling roadmap, and where also metal gates are used to replace poly-Si gate to avoid poly-depletion effects. Key in the success of this development is the electrical behavior of such high k/metal gate devices, and more specifically the Bias-Temperature- Instabilities, which are well-known reliability problems in MOS gate stacks. In this thesis, these Bias-Temperature effects will be investigated: the electrical behavior of the devices under Bias- Temperature stress will be characterized, models to explain the instability effects will be developed, the impact of processing, material composition and deposition techniques, annealing conditions etc. will be investigated, and ways to improve these BTI effects will be proposed. This work should ultimately lead to optimized gate stacks with higher BTI robustness

Autorentext

Marc Aoulaiche received the M.S. degree from the University of Provence (Aix-Marseille I), France, in 2004 and the PhD degree in microelectronics from the Interuniversity Microelectronics Center (IMEC), and Katholieke Universiteit Leuven, Belgium. Since January 2009, he has been with the Logic Device Design Group at IMEC.