Clock Generators for SOC Processors

This book explores the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. The text takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The comprehensive coverage includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.

Autorentext
Amr M. Fahim received his B.A.Sc, M.A.Sc, and Ph.D degrees from the University of Waterloo in Computer Engineering in 1996 and Electrical Engineering in 1997 and 2000, respectively. In 2000 he joined Qualcomm Inc., where he is currently working on the development of mixed-signal designs. He is the author of over 20 papers and 5 patents in this area, and has been a reviewer for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems II.

Klappentext

Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer's performance in the frequency domain, i.e. in terms of phase noise and spurious signals. As microprocessor frequency surges, the need to understand digital requirements for low-jitter and the design of low-jitter frequency synthesizers and clock generators becomes increasingly important. Clock Generators for SOC Processors is dedicated to the time-domain (i.e. jitter) design and analysis of frequency sythesizers and clock generators for microprocessor applications. In the past, such explanations have been scattered, and have not, to this date, been gathered into one comprehensive textbook.

Clock Generators for SOC Processors also focuses on the CMOS IC implementation of such synthesizers. An entire chapter is dedicated to low-voltage mixed-signal integrated circuit design in deep submicron CMOS technologies. Subsequent chapters discuss the design and analysis of the most common frequency synthesizer, the phase-locked loop (PLL), as well as state-of-the-art innovative architectures suitable for system-on-a-chip (SOC) processors. Design for Testability (DFT) is also discussed in the context of frequency synthesizers in SOC processors. The book concludes by discussing some of the most common issues that arise in clock interfacing, clock distribution, and accurate delay generation through delay-locked loops (DLLs) as they apply to SOC processors. Such issues mainly arise from having to communicate data and clock signals across multiple clock and power domains. Clock Generators for SOC Processors provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, and circuit level.

Inhalt
Phase-Locked Loop Fundamentals.- Low-Voltage Analog Cmos Design.- Jitter Analysis in Phase-Locked Loops.- Low-Jitter PLL Architectures.- Digital PLL Design.- DSP Clock Generator Architectures.- Design for Testability in PLLs.- Clock Partitioning and Skew Control.