CMOS Area Efficient Approximate Arithmetic Architectures

Approximate computation provide alternate solution to reduce energy consumption of high performance present day DSP application devices. Conventional multiplication and addition techniques consume a lot of energy. In this brief design of approximate arithmetic units for signal processing application is explored. First an approximate adder is proposed by changing the logic of basic full adder cell. The proposed adder cell has fewer transistor count compared to recent similar approach. Next, an approximate multiplier with low error is designed using lead one detection and selecting n/2 bits for an n bit input. The proposed n/2 bit approximate multiplier performs well in terms of error and power performance compared to recent similar approach. In continuation the approximate units are implemented in a Multiply-Accumulate(MAC) unit. The proposed approximate MAC unit provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Finally, the proposed MAC unit is implemented in filtering application to verify the functionality.

Autorentext

K.N. Vijeyakumar hat seinen Master of Engineering in Angewandter Elektronik an der GCT in Coimbatore abgeschlossen. Er hat seine Forschung im Bereich CMOS-Prozessordesign für Signal- und Bildverarbeitungsanwendungen abgeschlossen. Er hat Forschungsarbeiten in mehr als 27 Fachzeitschriften und auf 50 Konferenzen in den Bereichen Prozessordesign und Design von Bild- und Signalverarbeitungsanwendungen veröffentlicht.