CMOS SRAM Design and analysis of low leakage and high speed SRAM cell

In this work The novel single ended 5T and 6T SRAM cell is presented. This transistor is high density cell or takes less area than conventional 6T SRAM cell. Leakage current of this cell is very low as compared to other 5T or conventional 6T cell. There is a requirement of precharge circuit for this cell as that in conventional 6T SRAM cell. This cell is also power efficient. Also results show that the data stored in this cell is highly stable.There is always scope of improvement in any type of circuit or application. With the proposed configuration we can improve it with various techniques. We can change aspect ratio of the cell for better results. We can apply clock gating for power efficient circuit. We can improve peripheral circuit for better performance.

Autorentext

Rohin Gupta est chercheur au GNDEC, à Ludhiana, et président de la société Brainiac Solutions. Le professeur Sandeep Singh Gill est professeur et directeur du département ECE au GNDEC, Ludhiana. Navneet Kaur est professeur assistant au GNDEC, Ludhiana.