Code Based Test Data Compression for SoC Testing

To handle design complexity and short time-to-market, it has been common to use modular design approach in SoC. Such IP cores with hidden architecture have exaggerated the burning issues for fabrication testing of SoC: the test cost and test power. The cost of test is strongly related to the increasing test-data volumes which lead to longer test application times and larger tester memory. The solution is test data compression. The increasing test power leads to system reliability issues. The dynamic power which is is directly related to the number of transitions during scan operations plays a major role in overall test power. In this book, the test data compression and switching activity reduction in context of IP cores are addressed. For ATPG generated binary data with large number of don t care bits, run length codes and statistical codes are most suitable for IP cores. The switching activity reduction for external testing is suitable to IP cores for power reduction. If the don t care bit filling and reordering are used in synergy to pre-process the test data, the compression and power issues can be addressed without much on-chip area overhead.

Autorentext

Dr Usha Sandeep Mehta is presently working as Sr. Associate Professor at EC Dept, Nirma University, India. She did her M. Tech. and Ph. D. in the area 'VLSI Design'. She has published more than 50 research papers in various international/national journals/conferences. Her area of interest is Digital VLSI Design and VLSI Testing.