Compact Modeling for MOSFET Devices

Compact models of devices are used in circuit
simulators, in order to predict the functionality of
circuits. Multiple-gate devices will be preferred in
nanoscale circuits, thus calling for accurate and
reliable compact models, an important prerequisite
for successful circuit design.
In this book we present explicit compact charge and
capacitance models adapted for doped and undoped
devices (doped Double-Gate (DG) MOSFETs, undoped DG
MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and
undoped Surrounding-Gate Transistors (SGTs)). The
main advantage of our work is the analytical and
explicit character of the charge and capacitance
model that makes it easy to be implemented in
circuit simulators.
We also show the impact of important geometrical
parameters such as source and drain thickness, fin
spacing, spacer width, on the parasitic fringing
capacitance component of FinFETs and PI-gate
MOSFETs.

Autorentext

Oana Moldovan; PhD. in Electronics Engineering from Universitat
Rovira i Virgili, Spain. Postdoctoral researcher at the
Universitat Autònoma de Barcelona. Benjamin Iñiguez; PhD. in
Physics from the University of the Balearic Islands, Spain.
Titular Professor in the Department of Electronic Engineering,
Universitat Rovira i Virgili, Spain.

Klappentext

Compact models of devices are used in circuit
simulators, in order to predict the functionality of
circuits. Multiple-gate devices will be preferred in
nanoscale circuits, thus calling for accurate and
reliable compact models, an important prerequisite
for successful circuit design.
In this book we present explicit compact charge and
capacitance models adapted for doped and undoped
devices (doped Double-Gate (DG) MOSFETs, undoped DG
MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and
undoped Surrounding-Gate Transistors (SGTs)). The
main advantage of our work is the analytical and
explicit character of the charge and capacitance
model that makes it easy to be implemented in
circuit simulators.
We also show the impact of important geometrical
parameters such as source and drain thickness, fin
spacing, spacer width, on the parasitic fringing
capacitance component of FinFETs and PI-gate
MOSFETs.