Comparative analysis of Sequential and Concurrent processing for float

Floating point adders are hard to implement on reconfigurable devices because of complexity of their algorithm. Proposed work describes the implementation of floating point adder using sequential and concurrent processing on reconfigurable hardware. Implementation of floating point adder using sequential processing utilizes less chip area but with significant increase in combinational delay and clock period as compared with concurrent processing. Implementation of floating point adder using concurrent processing on Virtex 4 consumes 7% chip area with a combinational delay of 24.201nsec without offset and 27.891nsec offset delay and implementation of floating point adder on Spartan 2E using concurrent processing utilizes 401 slices with a combinational delay of 56.679nsec and consumes 188908 Kbytes of memory while implementing same on Spartan 2E using sequential processing consumes 52% chip area with a combinational delay of 69.987nsec and it implies that clock speed of concurrent processing is more than sequential processing but area consumption is also more.

Autorentext

Karan Gumber received the M.E. degree in electronics & comm. engineering from the UIET, Panjab University under the supervision of Sharmelee Thangjam. He is currently pursuing his Ph.D from IIT Roorkee under the supervision of Dr. Meeenaksi Rawat. His current research interests include signal processing for software defined radios, communications.