Comparison of Adiabatic and CMOS adders

Power minimization is one of the primary concerns in today VLSI design methodologies because of two main reasons one is the long battery operating life requirement of mobile and portable devices and second is due to increasing number of transistors on a single chip leads to high power dissipation and it can lead to reliability and IC packaging problems. This work mainly concentrates on low power circuit design approaches.this book covers 1.sources of power dissipation in CMOS logic 2.Adiabatic Logic Principle 3.Review of Adiabatic Logic families 4.Different full adder implementations

Autorentext

V.V.G.S Rajendra Prasad Completed his M.Tech from JNTU, Hyderabad. Presently he is working as Assitant professor in NOVA institute of tec-hnology and science,Andhrapradesh,India.Y.Sunil Gavaskar Reddy Completed his M.S from IIIT Pune.Presently he is working as a Assistant Professor in Anurag Engineering College, Andhrapradesh, India