Coupled Data Communication Techniques for High-Performance and Low-Power Computing

This overview of the circuits, architectures, and chip packaging for coupled data techniques discusses current research in chip-to-board capacitive coupling, chip-to-chip capacitive coupling, chip-to-chip inductive coupling, and chip-to-chip optical coupling.

Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.

Serves as a collection of the best-known-methods and ideas from leaders in the field. Includes a carefully-selected set of discussions on the important issues, tradeoffs, and techniques in coupled data I/O. Provides an overview of the circuits, architectures, and chip packaging for coupled data techniques. Covers the new and emerging area of coupled data communication. Includes supplementary material: sn.pub/extras

Klappentext
Designers of next-generation high-performance computer systems face a host of technical challenges. For the past several decades, rising clock frequencies and increased chip integration have fueled the growth of computer performance. Now these trends have slowed: power and complexity constrains further increases in clock frequencies, and economic realities limit the pace of Moore's Law. Coupled data communication provides a way forward, and this book, Coupled Data Communication Techniques for High-Performance and Low-Power Computing, gives a comprehensive overview for such coupled data techniques. Coupled data communication allows chips to communicatecapacitively or inductivelyover short distances between chips without solder, and fundamentally shifts the design paradigm from single-chip integration to single-package integration. This book covers the state-of-the-art in the circuits, architectures, and chip packaging for this novel chip-to-chip communication technology and showcases its potential to drive the coming decades of industry growth. Coupled Data Communication Techniques for High-Performance and Low-Power Computing should be of interest to students and designers in circuits and system architecture.

Inhalt
to Coupled Data Technologies.- Overview of 3D Technologies.- Power delivery, signaling and cooling for 2D and 3D integrated systems.- Coupled Data Technologies.- Capacitive Coupled Communication.- Inductive Coupled Communications.- Use of AC Coupled Interconnect in Contactless Packaging.- Enabling Coupled Data Technologies.- Aligning chips face-to-face for dense capacitive communication.- Extending Data Coupling Technologies.- Delivering On-chip Bandwidth Off-chip and Out-of-box with Proximity and Optical Communication.- AC Coupled Wireless Power Delivery.