Design a Reversible Fault Tolerant Programmable Array Logic

Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line pairs. In this thesis, we have proposed a structure which constructs Reversible Programmable Array Logic (RPAL).An algorithm has been proposed to reduce total number of gates, garbage outputs in the AND plane of a RPAL. We compare the existing AND plane with the proposed one using benchmark functions. We make the RPLA as fault tolerant. Our proposed design can realize ESOP (Exclusive Sum-of-Products) operations in terms of multi-output functions by using minimum number of gates, garbage outputs and quantum cost. In our design, we have used fault tolerant FRG (Fredkin Gate) and F2G (Feynman Double Gate) for making our RPAL Fault Tolerant. We have also proposed a non fault tolerant design for RPAL with the minimum number of gates, garbage outputs and quantum cost.

Autorentext

Md. Solaiman Mia received the B.Sc.(Hons.) and M.S. in the Dept. of Computer Science & Engineering from University of Dhaka, Bangladesh. He is currently working as a Lecturer with the Dept. of Computer Science & Engineering, Hamdard University Bangladesh. His research interests include Reversible Logic Synthesis, Quantum Computing etc.