Design and Analysis of Efficient Special Modern Adder

This book provides the basic idea of modern adder. The Full adder is the most important basic building block of the digital circuits employing arithmetic operation. It is more necessary to make these system more efficient to survive with high speed while consuming low power. The energy efficient designs have gained more recent attention and for highly utilized functional units, especially for the adders. The energy consumption of an adder depends on the circuit sizing, the recurrence structure and the wiring complexity. In VLSI circuits, such as Video Processing, Digital Signal Processing, Micro Processor uses Arithmatic opertions which are performed by full adder. The fundamental computational process encountered in digital system is binary addition, to accomplish the process binary adders are used, half adder and full adders are widely used to carry out binary addition . This paper presents a comparative analysis of design of 1-bit, 4-bit, 16-bit full adder and 4-bit subtractor using new technique and conventional technique. The design and simulation of full adder is performed in Cadence Design using Virtuoso.

Autorentext

M. K. Yogeshwaran travaillait comme professeur adjoint au département d'ingénierie électronique et de communication du KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore. Il est un individu accommodant et polyvalent avec 6 ans d'enseignement dans les cours UG et PG. Il a publié de nombreux articles dans des revues et conférences internationales.