Design and Development of Low Voltage Process Invariant SRAM Cell

Low read stability and high leakage current are two major problems in Static Random-Access Memory (SRAM) at the scaled CMOS technology node. This Book provides stability, leakage and process variation analysis of a Schmitt Trigger and read buffer based differential 10T (hereafter called ST3) SRAM cell. The ST3 cell provides improve read stability, tight Read Static Noise Margin (RSNM) distribution due to simultaneously implementation of Schmitt trigger and read buffer technique. Moreover, ST3 cell consumes low leakage current because of stack transistor technique and higher process tolerance due to simultaneously implantation of Schmitt trigger and read buffer techniques. This ST3 cell may be an attractive choice for battery-operated applications such as implantable medical device and remote sensor at the nm technology node.

Autorentext

Dr Amit Singh Rajput received his PhD in VLSI from Jiwaji University in 2019. His research interests are low power VLSI design, process invariant SRAM circuit, analog and digital integrated circuit design. Presently he is working with Microelectronics and VLSI Department, Chhattisgarh Swami Vivekanand Technical University, Bhilai, CG.