Design and Implementation of 5G algorithms on SIMD vector processor

With the wide spread of wireless technology, the time for 4G has arrived, and 5G will appear not so far in the future. However, no matter whether it is 4G or 5G, low latency is a mandatory requirement for baseband processing at base stations for modern cellular standards. In particular, in a future 5G wireless system, with massive MIMO and ultra-dense cells, the demand for low round trip latency between the mobile device and the base station requires a baseband processing delay of 1 ms. This is 10 percentage of today's LTE-A round trip latency, while at the same time massive MIMO requires large-scale matrix computations. This is especially true for channel estimation and MIMO detection at the base station. Therefore, it is essential to ensure low latency for the user data traffic. In this master's thesis, LTE/LTE-A uplink physical layer processing: channel estimation/MIMO detection are examined. The key aspect which affects the algorithms' speed is identified as the need for "massive complex matrix inversion". A parallel coding scheme is proposed to implement a matrix inversion kernel algorithm on a single instruction multiple data stream (SIMD) vector processor.

Autorentext

Jiabing Guo received his B.S degree from Savonia University of Appliced Sciences ,Kuopio, Finland, in 2011,and his M.S degree from Royal Institute of Technology, Stockholm, Sweden, in 2015. Now, he works as wireless protocol's software engineer in Datang Mobile Communication Equipment CO.LTD. His research interests include TD-LTE and future 5G.