Design and Implementation of Coding Algorithms for Network on Chip

Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve low latency , high throughput and optimal Energy-Performabilty trade-off. The proposed encoding and decoding scheme is applied to SOC architecture as a practical example. The proposed design improves error correction as compared to conventional schemes. The throughput of Butterfly fat tree(BFT)/BCH architecture is increased by 50%. The design decreases the latency of the network on chip by 30%. The total power consumption required to achieve the proposed design is slightly increased by 11%. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise effect (sN =0.135V) . At short wire lengths (0.05mm), BCH saves energy 5% while increasing perform-ability (0.9) and reliability.

Autorentext

Ayman Salem received the B.Sc. degree in Information Engineering and Technology and the Master degree in electronics engineering from German University in Cairo in 2010, 2014, respectively. His master thesis is in the area of Network on Chip and error correction coding schemes. His current research is focused on Network on Chip design, error correction coding schemes and low-power design. He is the author of three papers.