Design and Implementation of Floating Point Vedic Multiplier in VHDL

Multiplication is important operation in most of the signal processing applications.Hence,multiplier is the crucial part of signal processing applications like FIR filter,IIR filter,FFT,DFT,DCT etc.So,there is always need of a multiplier which is high speed,which consumes less area and low power.Hence performance of multiplier has direct effect on the final applications in which multipliers are used. In this book, we have tried to design optimized Vedic multiplier in HDL which can give good delay and area performance.As FIR,IIR filter have their coefficient in fraction,we have designed the multiplier in single precision floating point format. Hence,accuracy and range of multiplication coefficient is more. The Vedic multiplier is further used in FIR filer,IIR filter and Haar Wavelet transform as a basic building block.Also,it is compared with FIR filter,IIR filter and Haar Wavelet transform using other multipliers, such as Shift and Add multiplier,Array multiplier,and Wallace multiplier based on delay and area performance.

Autorentext

Kishor P. Upla is an Assistant Professor in S. V. National Instituteof Technology (SVNIT), Surat, Gujarat, India. He received his Ph.D.degree from Dhirubhai Ambani Institute of Information and Communicationtechnology (DA-IICT), Gandhinagar, India. His areas of interest includesignal and image processing including VLSI design.Prashant Howal received his M. Tech in VLSI & Embedded System Design from SVNIT, Surat. His area of research includes the design of VLSI andembedded systems.