Design and implementation of low power and high performance filter

Many creative thoughts for multipliers were proposed to improve performance. As the requirement for high speed processing has been expanding as an outcome of advancement in computer and signal processing services. For any processing applications, multipliers in association with adders were to be optimized. With the innovation in technology, the multiplier is designed to target any of these requirements satisfying increased speed, less power consumption and regularity of layout for a compact area suitable for high performance VLSI implementation

Autorentext

Dr. S. Jayakumar holds an engineering degree in Electronics and Instrumentation, master of engineering in Applied Electronics and completed doctorate in Information and communication engineering from Anna University Chennai. Has teaching experience more than 11 years in engineer and around placement training around 10 years.