Design of Prefix Adders Using Transmission Gate

The design of 64-bit parallel prefix adder using transmission gate which acquires least number of nodes with the lowest transistor count and low power consumption has been addressed in this book. The 64-bit parallel prefix adder is designed and comparison is made among previous parallel prefix adders. The result shows that the proposed 64-bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the speed. The proposed parallel prefix adders consumes less power and implements lesser number of transistors compared to existing parallel prefix adders.

Autorentext

Nehru Kandasamy got his Ph.D degree from Faculty of Information and Communication Engineering, Anna University, Chennai 2014. He is a Professor of the Department of Electronics and Communication Engineering at Institute of Aeronautical Engineering in Hyderabad. He is interested in Low Power VLSI, Quantum Cellular Automata and Memristor Designs.