Design, Simulation & HW Implementation of Sigma Delta Modulator

The overall objective of this book is to describe the Design, Simulate and Observe The hardware implementation of a multi stage low-pass sigma delta modulator. The objective of this book is shown first by describing a low-pass multistage for D/A Sigma Delta modulator. The next step involves a detailed evaluation of various accumulator based mash structures which is then modelled in MATLAB AND SIMULINK with the measurement of their characteristics and their non-idealties such as SNR ratio were calculated. The Final part of the report is to carefully evaluate the selected prototype of any cascaded stage say 1-1 MASH (multi stage noise shaping structure) under FPGA, The major application of Sigma Delta modulators is found to be in N-PLL frequency synthesizers, using error feed back topology sigma delta modulator, which eliminates the limit cycles oscillations and tones [4], the designing of such an accumulator in FPGA has been shown as the final or secondary goal for this report.

Autorentext

Dr. Kamel Mohammed Alikhan SIddiqui is the author of "Design, Simulation & HW Implementation of Sigma Delta Modulator".