Design & Analysis of Fast Adder using Quaternary Signed Digit (QSD)

Processors with high computational speed are necessary nowadays to solve problems faster and accurately. The speed of the processors depends on the speed of the basic processing unit. To increase the speed of these basic units we need fast adders and subtractors. This book discusses the QSD (Quaternary Sign Digit) adder unit which is faster than any other adders. The main problem of the adder is that the carry propagates from one stage to another increase. This can be reduced by using the QSD adder. It uses the base-four number system in which will help in reducing the number of bits required to store in the memory unit. This adder can be used for high-speed computing processors where the area is not a concern.

Autorentext

Dr. Ravi Shankar Mishra is working as Associate professor in School of Mechatronics Engineering in Symbiosis University of Applied Science (SUAS).Currently he is heading the Entrepreneurship cell of SUAS (SIMPRENUER) and various startups. He has more than 17 years of research and academic experience and worked with different academic institution.