Design & Performance Evaluation of Arithmetic Units in DSM

The core of every microprocessor, digital signal processor and data processing application-specific integrated circuit (ASIC) is its data path. It is often the crucial circuit component die area, power dissipation, and especially operation speed is of concern. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. It is also a very critical one if implemented in hardware because it involves an expensive carry-propagation step, the evaluation time of which is dependent on the operand word length. The efficient implementation is a key problem in VLSI design. As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage. This work presents the study on characterizing and analyzing the delay performance of various arithmetic units in CMOS digital circuits.

Autorentext

Autor Hiral Shah is working as an Application Engineer at Synopsys, Inc. CA-USA. She had done her Master's degree from CCET-GTU, Ahmedabad, Gujarat, India in Electronics and Communication (Major-VLSI). Her area of interests are in VLSI circuit design, Digital electronics circuit design in DSM, EDA tools, Low power Analysis etc.