Designing and Implementing Three dimensional Network on Chips

This book offers the help to find the way to implement a flexible three dimensional (3D) routing algorithm in comparison to the other implemented 3D routing algorithms. It also paves the road for the designer to find the optimal Three Dimensional Network on Chips (3D-NoCs) for each application and its specific requirements by creating automatically different 3D-NoCs. The 3D-NoCs are created by changing the number of tiers in the 3D system, number of routers per each tier and the two dimensional topology used in each tier through a tool that provided the 3D-NoC in synthesize able RTL files. By performing different experiments, a user can evaluate the 3D-NoCs across the most vital hardware aspects which are area, power consumption and latency. These 3D-NoCs can be created through an implemented open source tool. The book includes all the user needs to get all the benefits from the tool and how to use it effectively. And also the conception and the technology behind the implementation of the algorithm and the tool.

Autorentext

Masters and Bachelor of Microelectronics, Faculty of Engineering, Cairo University.Publications:M. Beheiry, A.Aly, H.Mostafa, and A.M.Soliman, Direct-Elevator: A modified routing algorithm for 3D-NoCs, in 2015 27th(ICM). M. Beheiry, H. Mostafa, Y. Ismail and A. M. Soliman, 3D-NOCET: A tool for implementing 3D-NoCs based on the Direct-Elevator