Development of Efficient Hardware Architecture for Image Compression

Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design of efficient hardware architectures for a fast computation of the transform has become imperative, especially for real-time applications. With this overall objective, the mapping of the computational tasks associated with the various resolution levels of the 5/3 DWT is first mathematically modeled, and then a modified computation of the DWT stages are explored from the standpoint of evading computing high frequency subbands. Furthermore, a Haar wavelet transform (HWT) is used for comparison. The proposed forward DWT (FDWT) and its inverse DWT (IDWT) hardware architecture filter generated similar results compared to the MATLAB model for the seven levels of DWT decomposition. Simulations were performed using grayscale images of different sizes to validate the proposed design and attain speed performance appropriate for a number of real-time applications.

Autorentext

Khamees Khalaf Hasan Al-jumaily, received the Bachelor's B.Sc. and Master M.Sc. degrees in Electrical Engineering and in Communication Engineering from University Of Technology in Baghdad, Iraq in 1985 and 2005, respectively. He completed his Ph.D. degree in image coding for FPGA applications, in June 2015 from Universiti Sains Malaysia USM.