Digital Design of SDRAM on Verilog

To design an 8 MB x 16 x 4-BAnk synchronous random access dynamic memory (SDRAM) (512 MB) using Verilog hardware description language, which can be used in any memory-based application. Today, computers, as well as other electronic systems that require large amounts of memory, use DRAMs for core memory. Due to the unique transistor cell structure of the DRAM, extremely dense memory networks can be constructed in a single device occupying a relatively small footprint. The conventional DRAM is controlled in an asynchronous manner, requiring the system designer to manually insert the standby states to meet the device specifications. Synchronization timing is dependent on DRAM speed and is independent of system bus speed. It is these limitations of synchronization that have led to the development of the SDRAM. The SDRAM is largely a fast DRAM with a high-speed synchronous interface. Input/output and controller signals are synchronized with an external clock, making new options available to the designer. Simplified interface circuits and high bandwidth data throughput can be obtained using SDRAM over conventional DRAM.

Autorentext

Abhishek Kumar é um autor técnico emergente. As suas principais áreas de investigação incluem a IoT, a aprendizagem automática e a computação em nuvem. Recebeu o prémio "Technical Genius Award" da Associação de Engenheiros e Técnicos Informáticos. Como investigador associado de um projeto financiado pelo DRDO, co-inventou o KGSAN (uma estrutura IoT premiada pelo Yahoo R&D).