Efficient Test Data Compression and Fault Analysis in VLSI Circuits

In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.

Autorentext

Sivaganesan S Received B.E in Electronics and Communication Engineering from VSB Engineering College, Karur and M.E in VLSI Design from Karpagam College of Engineering, Coimbatore, Presently Working as Assistant Professor in KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore. Published more number of papers in International level Journals